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information in eight bytes. There are also a number of new vectors not
familiar to the HC11 user. These are explained later.
Exception Routine There are many more interrupt sources possible in an HC16 system. To
Address allow maximum flexibility and maintain compatibility with the 68000
exception handling and external bus protocol, the internal peripherals do
not have fixed predetermined exception vectors like the HC11.
Each peripheral may have the exception vector number initialized after
reset, and it is up to the user to maintain these correctly. In addition, the
scheme allows any external device to be initialized with its own vector
number so there are no restrictions on the mix of peripheral devices.
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Application Note
Initialization of HC16 Device
User-Defined The user vector number is initialized for each module or interrupt source.
Vectors Some modules or submodules may have just a single vector, such as
the PIT, while others, such as the GPT, have 12 vectors associated with
the module. The vector number is an 8-bit value that, when multiplied by
2, becomes the vector address of the first exception vector for that
module or peripheral.
An example of the HC16 vector table is shown in Example 13. This
shows that for the GPT the vector number is set to $38 (decimal 56).
This can be compared with the definition of the HC11 and HC16 vector
tables that follow. Note the different start addresses and direction down
the vector table.
New Vectors The divide-by-zero interrupt is caused by a failure of the extended divide
for HC11 Users instructions from the CPU16. The bus error exception is explained in
External Hardware Interfacing, covering hardware design and
basically occurs as a result of a read of non-existent memory. The
breakpoint vector is associated with background mode. This leaves a
spurious interrupt where the SIM cannot determine the source of the
interrupt, the uninitialized interrupt, which is the default value for an
interrupt on 68000 peripheral devices and, finally, the autovectors. The
latter are most likely treated as XIRQ and IRQ pins by HC11 users.
These are directly linked to the IRQ1 to IRQ7 pins of the SIM and provide
the user with general-purpose interrupt vectors for non-68000 peripheral
devices.
Remember that the order of the vectors is not linked to the priority of the
interrupt and so, for example, the IRQ1 vector comes before the IRQ2
vector. There is, of course, a hierarchy of priorities for the exception
processing, and this can be found in the SIM reference manual.
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Application Note
Reset Status After a reset, this register can be checked to determine the source of the
Register reset for the HC16 device. This register is at $FFA06.
Sources of reset are:
" External reset
" Power-up reset
" Software watchdog reset
" Halt monitor reset
" Loss of clock reset
" System reset; from CPU32 and not available from CPU16
Example 12. Definition of HC11 Vector Table
ORG $FFD6
VECTORS
FDB SCI_interrupt ; SCI
FDB SPI_interrupt ; SPI
FDB PAC_interrupt ; PULSE ACC INPUT
FDB PAC_overflow ; PULSE ACC OVERFLOW
FDB OVERFLOW ; TIMER OVERFLOW 1
FDB IC4_INT ; INPUT CAPTURE 4 / OUTPUT COMPARE 5
FDB OC4_INT ; OUTPUT COMPARE 4
FDB OC3_INT ; OUTPUT COMPARE 3
FDB OC2_INT ; OUTPUT COMPARE 2
FDB OC1_INT ; OUTPUT COMPARE 1
FDB IC3_INT ; INPUT CAPTURE 3
FDB IC2_INT ; INPUT CAPTURE 2
FDB IC1_INT ; INPUT CAPTURE 1
FDB RTI ; REAL TIME INTERRUPT
FDB IRQ ; IRQ
FDB XIRQ ; XIRQ
FDB swi_interrupt ; SWI
FDB illegal ; ILLEGAL OPCODE
FDB cop_interrupt ; COP
FDB RESET ; CLOCK MONITOR
FDB RESET ; RESET
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Application Note
Initialization of HC16 Device
Table 13. Vector Table Definition for the HC16
Vector Vector SPACE
Exception
Number Address (prog/data)
0 0000 P Reset Initialize ZK, SK, PK
1 0002 P Reset Initial PC (start of user prog)
2 0004 P Reset Initialize SP
3 0006 P Reset Initialize IZ (direct page)
4 0008 D Breakpoint (BKPT)
5 000A D Bus error (BERR)
6 000C D Software interrupt (SWI)
7 000E D Illegal instruction
8 0010 D Divide by zero
9-14 0012 001C D Unassigned
15 001E D Uninitialized interrupt
16 0020 D Unassigned
17 0022 D Level 1 interrupt vector (autovector)
18 0024 D Level 2 interrupt vector (autovector)
19 0026 D Level 3 interrupt vector (autovector)
20 0028 D Level 4 interrupt vector (autovector)
21 002A D Level 5 interrupt vector (autovector)
22 002C D Level 6 interrupt vector (autovector)
23 002E D Level 7 interrupt vector (autovector)
24 0030 D Spurious interrupt
25 55 0032 006E D Unassigned
56 255 0070 01FE D User-defined interrupt vectors
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Application Note
Example 13. Actual HC16 Vector Table
org $0
k equ $0110 ; not used, zk=$1, sk=$1, pk=$0
sp equ {ramstart+$03fe} ; stack pointer starts at address $43fe
iz equ $0000 ; index pointer set for registers
org vectors
fdb k ; initial zk, sk, pk
fdb reset ; initial program counter value
fbd sp ; initial stack pointer value
fdb iz ; initial direct page select (iz)
fdb bkpt_int ; breakpoint address
fdb bus_err ; bus error address
fdb swi_int ; swi interrupt address
fdb illegal ; illegal instruction address
fdb div_by_0 ; divide by zero
dumy1 rmb 6 ;
dumy2 rmb 6 ;
fdb un-initialised ; uninitialised interrupt
fdb reset ; reserved
fdb int_1 ; level 1 interrupt autovector
fdb int_2 ; level 2 interrupt autovector
fdb int_3 ; level 3 interrupt autovector
fdb int_4 ; level 4 interrupt autovector
fdb int_5 ; level 5 interrupt autovector
fdb int_6 ; level 6 interrupt autovector
fdb int_7 ; level 7 interrupt autovector
fdb spurious ; spurious interrupt
end_main_vect equ *
org $70
fdb itic1 ; highest priority within GPT module
; - any of below can be selected
fdb itic1
fdb itic2
fdb itic3
fdb itoc1
fdb oc2_int
fdb itoc3
fdb itoc4
fdb iti4o5
fdb ioverflow
fdb ipulse_ovr
fdb ipactl ; lowest priority within GPT module
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Application Note
Exception Handling (Interrupts)
Exception Handling (Interrupts)
Interrupt Request Interrupts are called exceptions in the HC16 world. This conforms to the
Handling nomenclature of the 68000 processor and more accurately explains the
nature of the sudden change in the activities of the CPU. Interrupts will,
therefore, be referred to as exceptions from now on.
Module Design Many of the HC16 modules are clearly based on the functionality of an
Influence HC11 module. A prime example of this is the general-purpose timer
on the Conversion (GPT) timer module. The main difference lies in the IMB interface and
from HC11 this required some specific initialization of the interrupt vectors,
to HC16 Code arbitration, etc. After this, there is often a modulus prescaler where the
HC11 had a choice of just divide-by-two options before and this is
necessary to accommodate the variable system clock frequency
possible with the PLL. In addition to this, the module may also operate
at higher maximum speeds, greater functionality, and generally be more
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